1. Field of the Invention
The present invention relates to a gate signal line driving circuit and a display device using the same. More particularly, the invention relates to suppression of changes in the threshold voltage of the switching elements of a gate signal line driving circuit and improvement in the display performance of a display device using the switching elements.
2. Description of the Related Art
In display devices such as liquid crystal display devices, there are cases where a display device with an internal shift register has been adopted. The display device with an internal shift register has a configuration in which shift register circuits provided in a gate signal line driving circuit that scans gate signal lines are formed on the same substrate as a thin film transistor (hereinafter referred to as a TFT) disposed on a pixel region of a display screen. A shift register circuit according to the related art is disclosed in JP 2007-95190 A.
Each of a plurality of fundamental circuits that constitute the shift register circuits provided in a gate signal line driving circuit output a high voltage to a gate signal line as a gate signal Gout in a gate scanning period (hereinafter referred to as a signal high period) during one frame period, corresponding to a gate signal line to which a gate signal is output from the fundamental circuit, and outputs a low voltage to the gate signal line as a gate signal Gout in a period other than the gate scanning period (hereinafter referred to as a signal low period).
FIG. 14 is a schematic diagram showing a simplified configuration of a fundamental circuit of a shift register circuit according to the related art. The fundamental circuit of the shift register circuit includes a low voltage application switching element SWA that outputs a low voltage to a gate signal line in response to a signal low period and a high voltage application switching element SWG that outputs a high voltage to a gate signal line in response to a signal high period.
A low voltage line VGL is connected to the input side of the low voltage application switching element SWA. The low voltage application switching element SWA is turned ON and a low voltage which is the voltage of the low voltage line VGL is output as the gate signal Gout in response to the start of the signal low period so that a low voltage is output stably as the gate signal Gout during the signal low period. Moreover, the low voltage application switching element SWA is turned OFF in response to the start of the signal high period. A node at which a voltage is applied to the switch of the low voltage application switching element SWA will be denoted as a node N2. During a period when the low voltage application switching element SWA is in the ON state, the node N2 is changed so as to have a high voltage, and a high voltage is applied to the switch of the low voltage application switching element SWA. Furthermore, during a period when the low voltage application switching element SWA is in the OFF state, the node N2 is changed so as to have a low voltage, and a low voltage is applied to the switch of the low voltage application switching element SWA.
A fundamental clock signal CLK is input to the input side of the high voltage application switching element SWG. The high voltage application switching element SWG is turned ON and the voltage of the fundamental clock signal CLK is output as the gate signal Gout in response to the signal high period so that a high voltage is output to the corresponding gate signal line in the signal high period.
Here, the fundamental clock signal CLK is at a high voltage during the signal high period. Moreover, the high voltage application switching element SWG is turned OFF in response to the signal low period, and the signal of the fundamental clock signal CLK is cut and is not output. A node at which a voltage is applied to the switch of the high voltage application switching element SWG is denoted as a node N1. During a period when the high voltage application switching element SWG is in the ON state, the node N1 is at a high voltage, and a high voltage is applied to the switch of the high voltage application switching element SWG. Furthermore, during a period when the high voltage application switching element SWG is in the OFF state, the node N1 is at a low voltage, and a low voltage is applied to the switch of the high voltage application switching element SWG.
A switching signal supply switching element SWB that supplies a low voltage in response to the signal low period is connected to the switch of the high voltage application switching element SWG. The low voltage line VGL is connected to the input side of the switching signal supply switching element SWB, and thus, in response to the signal low period, the switching signal supply switching element SWB is turned ON, the node N1 is changed so as to have a low voltage, and a low voltage is applied to the switch of the high voltage application switching element SWG. Moreover, the switching signal supply switching element SWB is turned OFF in response to the signal high period. The voltage of the node N2 is supplied to the switch of the switching signal supply switching element SWB similarly to the switch of the low voltage application switching element SWA. As described above, during a period when the switching signal supply switching element SWB is in the ON state, the node N2 is at a high voltage and a high voltage is applied to the switch of the switching signal supply switching element SWB.
FIG. 15 is a circuit diagram showing an example of the fundamental circuit of the shift register circuit according to the related art. In FIG. 15, a transistor T6 provided in a low voltage application switching circuit 211 corresponds to the low voltage application switching element SWA. Similarly, a transistor T5 provided in a high voltage application switching circuit 212 corresponds to the high voltage application switching element SWG. In addition, a transistor T2 provided in a switching signal supply switching circuit 213 corresponds to the switching signal supply switching element SWB.
A step-up capacitor C1 provided between the gate and source electrodes of the transistor T5 has a function of applying a bootstrap voltage to the gate electrode when a high voltage is applied to a gate signal Gn and suppressing deformation of a waveform.
During the signal low period, a high voltage is periodically supplied from the transistor T3, and the high voltage is held in a holding capacitor C3, whereby the node N2 is maintained at the high voltage. The transistor T6 is turned ON by the high voltage of the node N2, and the low voltage of the low voltage line VGL is output through an output terminal OUT as the gate signal Gn. Moreover, the transistor T2 is also turned ON, and the node N1 is held at the low voltage of the low voltage line VGL.
On the other hand, the transistor T1 is turned ON in response to the signal high period by a gate signal Gn−1 of a fundamental circuit on the previous stage, which is input to an input terminal IN3, and the node N1 is changed so as to have a high voltage. Accordingly, the voltage of a fundamental clock signal Vn input through an input terminal IN1 is output through the output terminal OUT as the gate signal Gn. Moreover, the transistor T7 is turned ON by the gate signal Gn−1, whereby the node N2 is changed so as to have a low voltage. After that, when the node N1 is changed so as to have a high voltage, the transistor T4 is turned ON, whereby the node N2 is maintained at the low voltage of the low voltage line VGL. After that, when another signal low period comes again, a transistor T9 is turned ON by a gate signal Gn+2 supplied through the input terminal IN4, and the node N1 is changed so as to have a low voltage. The above-described operation is repeated.
That is, the nodes N1 and N2 are maintained at the low and high voltages, respectively, in response to the signal low period and are changed so as to have the high and low voltages, respectively, in response to the signal high period.
Moreover, the potentials of the nodes N1 and N2 are unstable at the startup of the display device. A startup reset transistor T10 is provided between the node N2 and a high voltage line VGH, so that when the transistor T10 is turned ON by an auxiliary signal VST at the time of startup, the node N2 is changed so as to have a high voltage, and the circuit is initialized. In this configuration, when the node N2 is changed so as to have the high voltage, the node N1 is also initialized with the low voltage.
A phenomenon called Vth shift where a threshold voltage Vth of a transistor changes in accordance with the relationship of voltages applied to the respective electrodes of the transistor exists. The Vth shift occurs under conditions where the proportion of a period where a high voltage is applied to the gate electrode and a low voltage is applied to at least one of the source and drain electrodes is large. The Vth shift occurs also under conditions where the proportion of a period where a low voltage is applied to the gate electrode and a high voltage is applied to at least one of the source and drain electrodes is large.
In the startup reset transistor, an OFF voltage (a low voltage in the example of FIG. 15) is applied to the gate electrode thereof during a period other than the startup, namely the majority period, and an ON voltage (a high voltage in the example of FIG. 15) is applied to the drain electrode thereof. Thus, the Vth shift occurs, and the threshold voltage Vth of the transistor is shifted. In the example of FIG. 15, the threshold voltage Vth is shifted to a negative direction. Thus, off-leakage, malfunctioning, and the like are likely to occur, which may cause deterioration of a display performance.
Moreover, for example, when the Vth shift occurs in the low voltage application switching element SWA and the like and the threshold voltage Vth thereof exceeds a critical value, the low voltage application switching element SWA is not sufficiently turned ON in response to the signal low period. Thereupon, a sufficiently low voltage is not output to the gate signal, and noise is superimposed on the gate signal. Moreover, when the threshold voltage Vth of the switching signal supply switching element SWB exceeds a critical value, the switching signal supply switching element SWB is not sufficiently turned ON in response to the signal low period, and a sufficiently low voltage cannot be applied to the node N1. Thus, the transistor T5 is not sufficiently turned OFF, and a part of the fundamental clock signal CLK is applied to the gate signal as noise.
When noise is superimposed on the gate signal, even during the signal low period, a display data voltage which should be written to other pixels is written to pixels connected to the gate signal line, and a display performance deteriorates.